The present invention relates to an interface circuit for an information processing device.
Each of FIGS. 1 and 2 shows a conventional interface circuit for an information processing device. FIG. 1 shows an example for driving the total system with a single power source. FIG. 2 shows another example for driving the total system with discrete power sources particular to the respective units.
Throughout the drawings, an interface line 11, units 12, power sources 13 and buffers 14 are provided.
In FIG. 2, a plurality of input/output signals are generated by a plurality of units 12 on their respective signal lines 11a of the interface line 11 while being powered with the respective power sources 13.
FIG. 3 shows an example of one of the buffers 14 as included in the system of FIG. 2.
In FIG. 3, output sides 1-3 and input sides 4-6 of said buffer 14 communicate via the interface line 11. From the output sides 1-3, the open-collector output signals OC are wired-OR and end at one of the input sides 4-6 with an termination resistor R.
Therefore, conventionally, the termination resistor R is needed to thereby provide a large loss current and prevent the desired sharp wave form. When the system capacity is to be expanded, the provision of an additional termination resistor R is needed. When a termination resistor does not have a voltage supplied thereto, the total system is inoperative.
Therefore, it is desired to provide an improved interface circuit for eliminating the above problems.